Benchmarks on building the training models

Benchmarks were run on the compute nodes of Cascade Lake microarchitecture (Intel Xeon Gold 6248 CPU@2.50GHz). The HIBAG package was compiled with GCC v8.3.0 in R-v4.0.2. In HIBAG (>= v1.26.1), users can use hlaSetKernelTarget() to select the target intrinsics, or hlaSetKernelTarget("max") for maximizing the algorithm efficiency.

GCC (>= v6.0) is recommended to compile the HIBAG package. In the benchmarks, the kernel version of HIBAG_v1.24 is v1.4, and the kernel version of newer package is v1.5.

# continue without interrupting
IgnoreError <- function(cmd) tryCatch(cmd, error=function(e) { message("Not support"); invisible() })
IgnoreError(hlaSetKernelTarget("sse4"))
## [1] "64-bit, SSE4.2, POPCNT"                                               
## [2] "13.2.0, GNUG_v13.2.0"                                                 
## [3] "Algorithm SIMD: SSE2 SSE4.2 AVX AVX2 AVX512F AVX512BW AVX512VPOPCNTDQ"
IgnoreError(hlaSetKernelTarget("avx"))
## [1] "64-bit, AVX"                                                          
## [2] "13.2.0, GNUG_v13.2.0"                                                 
## [3] "Algorithm SIMD: SSE2 SSE4.2 AVX AVX2 AVX512F AVX512BW AVX512VPOPCNTDQ"
IgnoreError(hlaSetKernelTarget("avx2"))
## [1] "64-bit, AVX2"                                                         
## [2] "13.2.0, GNUG_v13.2.0"                                                 
## [3] "Algorithm SIMD: SSE2 SSE4.2 AVX AVX2 AVX512F AVX512BW AVX512VPOPCNTDQ"
IgnoreError(hlaSetKernelTarget("avx512f"))
## [1] "64-bit, AVX512F"                                                      
## [2] "13.2.0, GNUG_v13.2.0"                                                 
## [3] "Algorithm SIMD: SSE2 SSE4.2 AVX AVX2 AVX512F AVX512BW AVX512VPOPCNTDQ"
IgnoreError(hlaSetKernelTarget("avx512bw"))
## [1] "64-bit, AVX512BW"                                                     
## [2] "13.2.0, GNUG_v13.2.0"                                                 
## [3] "Algorithm SIMD: SSE2 SSE4.2 AVX AVX2 AVX512F AVX512BW AVX512VPOPCNTDQ"

The CPU may reduce the frequency of the cores dynamically to keep power usage of AVX512 within bounds, hlaSetKernelTarget("auto.avx2") can automatically select AVX2 even if the CPU supports the AVX512F and AVX512BW intrinsics. Please check the CPU throttling with AVX512 intrinsics.

1) Speedup factor using small training sets

2) Speedup factor using medium training sets

3) Speedup factor using large training sets

Multithreading

The multi-threaded implementation can be enabled by specifying the number of threads via nthread in the function hlaAttrBagging(), or hlaParallelAttrBagging(cl=nthread, ...).

Here are the performance of multithreading and the comparison between AVX2 and AVX512BW: